Agnify

HDL Courses

Introduction to Verilog for RTL Design (#VER01)

A 3 day course teaching designers to write efficient, accurate RTL code for synthesis as well as basic testbenching and verification techniques.

Introduction to VHDL for RTL Design (#VHD01)

A 4 day course teaching designers to write efficient, accurate RTL code for synthesis as well as basic testbenching and verification techniques.

Advanced VHDL (#VHD02)

A 3 day course emphasizing behavioral techniques, testbench strategies and design management.
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